rtl-design-engineer

SKILLWorkflowCommunity
v0.0.0Mr-Fang-VLSIMITAktualisiert vor 3 Mon.Quelle →

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

Community-submitted skill. Not yet reviewed by the Forge team. Full prompt content may not be available.Request review →
8Repo-Sterne
1Clients
1Formate
vor 3 Mon.Letzte Aktualisierung
Skill
AutorMr-Fang-VLSI
Version0.0.0
LizenzMIT
KategorieWorkflow
Formateskill.md
PromptNicht veröffentlicht
Kompatibilität
Claude✓ Unterstützt
Cursor
Copilot
ChatGPT
Gemini
Über

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

Schlagwörter
skillclaude