rtl-design-engineer

SKILLFlujo de trabajocomunidad
v0.0.0Mr-Fang-VLSIMITActualizado hace 3 mFuente →

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

Community-submitted skill. Not yet reviewed by the Forge team. Full prompt content may not be available.Request review →
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hace 3 mÚltima actualización
Skill
AutorMr-Fang-VLSI
Versión0.0.0
LicenciaMIT
CategoríaFlujo de trabajo
Formatosskill.md
PromptNo publicado
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Claude✓ Compatible
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Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

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