rtl-design-engineer

SKILLWorkflowcommunauté
v0.0.0Mr-Fang-VLSIMITMis à jour il y a 3 moisSource →

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

Community-submitted skill. Not yet reviewed by the Forge team. Full prompt content may not be available.Request review →
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il y a 3 moisDernière mise à jour
Skill
AuteurMr-Fang-VLSI
Version0.0.0
LicenceMIT
CatégorieWorkflow
Formatsskill.md
PromptNon publié
Compatibilité
Claude✓ Pris en charge
Cursor
Copilot
ChatGPT
Gemini
À propos

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

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