rtl-design-engineer

SKILLFlusso di lavorocommunity
v0.0.0Mr-Fang-VLSIMITAggiornato 3 mesi faFonte →

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

Community-submitted skill. Not yet reviewed by the Forge team. Full prompt content may not be available.Request review →
8Stelle del repo
1Client
1Formati
3 mesi faUltimo aggiornamento
Skill
AutoreMr-Fang-VLSI
Versione0.0.0
LicenzaMIT
CategoriaFlusso di lavoro
Formatiskill.md
PromptNon pubblicato
Compatibilità
Claude✓ Supportato
Cursor
Copilot
ChatGPT
Gemini
Descrizione

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

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