Compiler-backed read-only Verilog and SystemVerilog project analysis.
is a local Model Context Protocol server that gives AI agents compiler-backed, read-only context for Verilog and SystemVerilog projects. It wraps so an MCP client can ask questions against parsed and elaborated HDL instead of plain text: What modules, interfaces, and packages are in this filelist? What diagnostics does the compiler frontend report? What is the instance hierarchy below this top?…
Verification confirms publisher identity (repo ownership), not code safety. The security scan covers known CVEs and suspicious install scripts — it cannot prove the absence of malicious code.
is a local Model Context Protocol server that gives AI agents compiler-backed, read-only context for Verilog and SystemVerilog projects. It wraps so an MCP client can ask questions against parsed and elaborated HDL instead of plain text: What modules, interfaces, and packages are in this filelist? What diagnostics does the compiler frontend report? What is the instance hierarchy below this top? Where is this symbol declared or referenced? Did my include paths, defines, and nested files resolve…