rtl-design-engineer

SKILLWorkflowcommunity
v0.0.0Mr-Fang-VLSIMITUpdated 5mo agoSource →

Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

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5mo agoLast update
Skill
AuthorMr-Fang-VLSI
Version0.0.0
LicenseMIT
CategoryWorkflow
Formatsskill.md
PromptNot published
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Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

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skillclaude

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