Adversarial, structured review of RTL (Verilog/SystemVerilog) changes: timing risk, maintainability, synthesis-friendliness, interface consistency, with severity grading and a pass/fail gate. Use when the user asks to review RTL changes, run a code review before commit/delivery, or do a reliability
Adversarial, structured review of RTL (Verilog/SystemVerilog) changes: timing risk, maintainability, synthesis-friendliness, interface consistency, with severity grading and a pass/fail gate. Use when the user asks to review RTL changes, run a code review before commit/delivery, or do a reliability check on hardware code. 触发词: "检查 rtl", "检查RTL", "检查 RTL", "帮我检查 rtl", "rtl review", "code review", "
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