Static signal-path tracing and module-dependency analysis for Verilog/SystemVerilog projects: trace a signal from source to sink across module hierarchy, flag clock-domain crossings, and build module dependency graphs to validate file lists (file_list.f). Text-search based, no EDA or AST tooling req
Static signal-path tracing and module-dependency analysis for Verilog/SystemVerilog projects: trace a signal from source to sink across module hierarchy, flag clock-domain crossings, and build module dependency graphs to validate file lists (file_list.f). Text-search based, no EDA or AST tooling required. Use when the user asks to trace a signal, analyze CDC risk, map module call/instantiation rel
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