Single-source register map pipeline: keep one regmap.md per module as the source of truth, generate register documentation (Markdown + CMSIS-SVD) and SystemVerilog assertions (reset / RO / W1C / reserved / address-range) from it, and check RTL vs. register map consistency. Use when the user adds or
Single-source register map pipeline: keep one regmap.md per module as the source of truth, generate register documentation (Markdown + CMSIS-SVD) and SystemVerilog assertions (reset / RO / W1C / reserved / address-range) from it, and check RTL vs. register map consistency. Use when the user adds or modifies register definitions, asks for register docs/assertions, or wants RTL-to-register-map consi
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